As devices become smaller and integration density increases, high density plasma chemical vapor deposition (HDP-CVD) has become a key process due in back filling high aspect ratio features such as shallow trench isolation (STI) features due to its superior gap-filling capability. In particular, high density plasma (HDP) processes, such as electron cyclotron resonance (ECR) processes and inductively coupled plasma (ICP) processes have been found to produce high-quality field oxides. Generally, HDP-CVD provides a high density of low energy ions resulting in higher quality films at lower deposition temperatures, compared to other plasma enhanced CVD deposition processes such as PECVD.
In a HDP-CVD deposition process, for example, a bias power is coupled to the semiconductor wafer to attract ions which sputter (etch) the wafer during deposition (re-sputtering effect), thereby preventing a phenomenon known as crowning where the deposition material converges over the trench before an etched feature opening is completely filled with the deposition material. The deposition rate may therefore be more finely tuned to improved CVD deposition properties to, for example, avoid crowning.
As device sizes decrease below 0.13 micron critical dimension, however, the gap fill of openings, for example STI openings, becomes problematical and the process window for successful gap filling is narrowed. Generally, as device sizes decrease and aspect ratios increase to greater than about 4 to 1, relatively high plasma RF powers, for example, greater than about 6 Watts/cm2 are delivered to a process water surface creating relatively large thermal stresses during the gap filling desposition. To maintain lower deposition temperatures the backside of the water is frequently cooled, leading to increased thermal gradients and consequently stresses across the wafer surface and through the wafer thickness. Consequently, compressive stresses, relatively larger parallel to the wafer process surface, are generated following the HDP-CVD process loading to subsequent problems in device quality and reliability. For example, charge carrier mobilities are strongly influenced, e.g., decreased due to stresses fields present in semiconductor materials.
There is therefore a need in the integrated circuit manufacturing art to develop an improved method for filling gaps including shallow trench isolation (STI) structures as well as a STI structure having reduced stresses to achieve improved semiconductor device quality and reliability.
It is therefore among the objects of the present invention to improved an improved method for filling gaps including shallow trench isolation (STI) structures as well as forming a STI structure having reduced stresses to achieve improved semiconductor device quality and reliability, in addition to overcoming other shortcomings and deficiencies of the prior art.